Pipelining & Hazards (Quick Summary)

1. Pipelining

This is a technique that allows the CPU to process multiple instructions simultaneously (Instruction-Level Parallelism), similar to an "assembly line in a factory."

• Traditional (Non-Pipelined): Must wait for instruction 1 to complete all 4 stages (Fetch, Decode, Execute, Store) before starting instruction 2.
• Pipelined: While instruction 1 is executing, instruction 2 can decode, and instruction 3 can fetch concurrently in the same Clock Cycle, significantly increasing throughput.

2. Pipeline Hazards (Problems that disrupt the pipeline)

When instructions overlap, problems may occur that cause the pipeline to stall (Stall / Bubble).

1. Structural Hazard: Insufficient resources (e.g., trying to use the same memory to read an instruction and read data simultaneously).
   • Solution: Separate Cache into Instruction Cache and Data Cache.
2. Data Hazard: Instruction 2 requires the result from instruction 1, but instruction 1 has not finished processing yet.
   • Solution: Use Data Forwarding (bypassing the result directly from the ALU circuit back without waiting to write to the Register).
3. Control Hazard (Branch Hazard): Occurs when encountering an if-else or jump instruction, causing the CPU to not know which path to fetch for the next instruction.
   • Solution: Use Branch Prediction (predicting the path in advance, and if guessed wrong, flush the pipeline).